Program circuit suppressing stand-by current and permitting highly reliable operation, and semiconductor memory device using the program circuit

ABSTRACT

An inverter receives a reset signal output from a reset signal generating circuit, and drives a potential level of a first internal node according to whether a fuse element is blown or not. A transfer gate is provided between the first internal node and a second internal node and drives the first internal node and the second internal node to either a conductive state or a shutdown state according to a delayed reset signal from the reset signal generating circuit. A latch circuit is provided between the second internal node and an output node, and latches a potential level of the second internal node and outputs an inverted level of the potential level of the second internal node to the output node.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a program circuit capable of recordingdata in a non-volatile manner and a configuration of a semiconductormemory device using the same program circuit. More particularly, thepresent invention relates to a program circuit that is applied to asemiconductor memory device including a redundant circuit and aconfiguration of a semiconductor memory device having such a programcircuit.

2. Description of the Background Art

FIG. 17 is a block diagram showing a configuration of a main portion ofa conventional semiconductor memory device that includes a redundantcircuit.

A memory cell array 1 includes a plurality of word lines WL, a pluralityof bit line pairs BL crossing the plurality of word lines WL, and aplurality of memory cells MC provided at the respective crossing pointsof word lines WL and bit line pairs BL. Memory cell array 1 furtherincludes a redundant word line RWL and a plurality of memory cells MCconnected to the redundant word line RWL.

A decoder 2 and a sense amplifier unit 13 are connected to memory cellarray 1. Sense amplifier unit 13 includes a plurality of senseamplifiers connected to the plurality of bit line pairs BL, a pluralityof transfer gates, and a decoder.

This semiconductor memory device is provided with a replacement circuit10. Replacement circuit 10 includes a redundancy select circuit 3, areplacement address program circuit 4 and a NAND circuit 5. Replacementcircuit 10 and redundant word line RWL constitute a redundancy circuit.

An operation of the semiconductor memory device shown in FIG. 17 willnow be described.

Decoder 2 responds to an X address signal XA and selects one of theplurality of word lines WL within memory cell array 1, and raises thepotential of the selected word line WL to an H level. Thus, data areread out from memory cells MC connected to the selected word line WL tocorresponding bit line pairs BL. The data thus read out are amplified bythe sense amplifiers provided in sense amplifier unit 13. The decoder insense amplifier unit 13 responds to a Y address signal YA and rendersone of the plurality of transfer gates conductive. As a result, onepiece of data is output.

If there is a defect associated with a certain word line WL, redundantword line RWL is used instead of that word line WL. In this case, theoutput of redundancy select circuit 3 attains an H level. An address ofthe word line WL to be replaced is programmed in replacement addressprogram circuit 4.

If an address designated by X address signal XA matches the address(replacement address) programmed in replacement address program circuit4, then the output of replacement address program circuit 4 attains an Hlevel. When the outputs of redundancy select circuit 3 and replacementaddress program circuit 4 both attain an H level, the output of NANDcircuit 5 (a decoder inactivation signal DA) attains an L level. Thus,the decoder becomes inactive, and all the word lines WL enter anunselected state. The potential of redundant word line RWL rises to an Hlevel.

Thus, in response to a defective word line WL or a word line WLconnected to a defective memory cell MC having been selected, redundantword line RWL is selected instead of the word line WL.

Although not shown in FIG. 17, memory cell array 1 may include aredundant bit line pair.

FIG. 18 is a circuit diagram illustrating a configuration of a fuseprogram circuit 810 included in redundancy select circuit 3.

Referring to FIG. 18, fuse program circuit 810 includes a fuse elementF1 provided between a node N1 and a power supply potential Vcc; a MOScapacitor C1 provided between node NI and a ground potential GND; an Nchannel MOS transistor QN1 provided between node N1 and a groundpotential GND; and an inverter INV1 that receives and inverts thepotential of node N1 and supplies its output to a gate of transistorQN1.

The potential at an output node N2 of inverter INV1 becomes an outputlevel of fuse program circuit 810, and this output level in turn becomesan output level of redundancy select circuit 3. Thus, the output levelof fuse program circuit 810 is at an L level when a fuse is not blownand at an H level when the fuse is blown.

In a normal mode, i.e., when redundant word line RWL is not in use(referred to as a “redundancy non-selected mode”), fuse F1 is connected.Thus, the potential of node N2 is at a ground level, and a signal of anL level is input to NAND circuit 5 in FIG. 17. As a result, decoderinactivation signal DA attains an H level, and the potential ofredundant word line RWL remains inactive.

When redundant word line RWL is to be used (referred to as a “redundancyselected mode”), fuse F1 is blown. At power-on, the potential of node N2starts to rise towards an H level because of capacitive coupling by theMOS capacitor C1. Further, the potential of node N2 reaches a complete Hlevel by a positive feedback circuit consisting of transistor QN1 andinverter INV1.

Accordingly, in the redundancy non-selected mode, the output ofredundancy select circuit 3 attains an L level; whereas, in theredundancy selected mode, it attains an H level.

FIG. 19 is a circuit diagram illustrating a detailed configuration ofreplacement address program circuit 4. An address setting circuit 40includes a fuse F11, a MOS capacitor C11, an N channel MOS transistorQN11 and an inverter INV11. An address setting circuit 50 includes afuse F12, a MOS capacitor C12, an N channel MOS transistor QN12 and aninverter INV12. The configuration and operation of each of addresssetting circuits 40 and 50 are similar to those of fuse program circuit810 included in redundancy select circuit 3 shown in FIG. 18.

Thus, the potential at node N21 of address setting circuit 40 attains anL level when fuse F11 is connected and an H level when fuse F11 isblown. Similarly, the potential at node N22 of address setting circuit50 is at an L level when fuse F12 is connected and at an H level whenfuse F12 is blown.

Between an input terminal I1 and an output terminal O1 are connected Pchannel transistors 61, 62 and N channel transistors 71, 72. Similarly,P channel transistors 63, 64 and N channel transistors 73, 74 areconnected between an input terminal I2 and output terminal O1; P channeltransistors 65, 66 and N channel transistors 75, 76, between an inputterminal I3 and output terminal O1; and P channel transistors 67, 68 andN channel transistors 77, 78, between an input terminal I4 and outputterminal O1.

The gate electrodes of transistors 61, 73, 65, 77 are connected to nodeN21 of address setting circuit 40. The gate electrodes of transistors71, 63, 75, 67 are connected to node N1 of address setting circuit 40.The gate electrodes of transistors 62, 64, 76, 78 are connected to nodeN22 of address setting circuit 50. And the gate electrodes oftransistors 72, 74, 66, 68 are connected to node N12 of address settingcircuit 50.

Pre-decode signals, obtained by pre-decoding X address signals XA, areprogrammed in replacement address program circuit 4 shown in FIG. 19.The way of programming in program circuit 4 will now be described.

First, pre-decode signals X0·X1, X0·/X1, /X0·X1, /X0·/X1 are defined asfollows:

If X0=H level and X1=H level, then X0·X1=H level;

If X0=H level and X1=L level, then X0·/X1=H level;

If X0=L level and X1=H level, then /X0·X1=H level; and

If X0=L level and X1=L level, then /X0·/X1=H level.

Under the conditions other than the above, pre-decode signals X0·X1,X0·/X1, /X0·X1 and /X0·/X1 each attain an L level.

Here, assume that pre-decode signal X0·X1 is applied to input terminalI1, pre-decode signal X0·/X1 to input terminal I2, pre-decode signal/X0·X1 to input terminal I3, and pre-decode signal /X0·/X1 to inputterminal I4.

When fuses F11, F12 are both connected, only input terminal I1 isconnected to output terminal O1, and accordingly, pre-decode signalX0·X1 appears at output terminal O1. Thus, the output at the time whenX0=H level and X1=H level becomes an H level, and at this time,redundant word line RWL is selected. This means that an address ofX0=X1=H level has been programmed to replacement address program circuit4 by fuses F11 and F12.

When fuse F11 is blown or disconnected and fuse F12 is connected,pre-decode signal X0·/X1 appears at output terminal O1. Thus, an addressof X0=H level and X1=L level is programmed. When fuse F11 is connectedand fuse F12 is disconnected, pre-decode signal /X0·X1 appears at outputterminal O1. Thus, an address of X0=L level and X1=H level isprogrammed. When fuses F11 and F12 are both blown, pre-decode signal/X0·/X1 appears at output terminal O1. Thus, an address of X0=X1=L levelis programmed.

Replacement address program circuit 4 shown in FIG. 19 is provided withfour pre-decode signals X0·X1, X0·/X1, /X0·X1 and /X0·/X1 obtained bypre-decoding two X address signals X0 and X1. Since there are normallyfour or more X address signals, a plurality of circuits each as shown inFIG. 19 are provided, with their outputs being input into NAND circuit 5shown in FIG. 17.

With the configuration as described above, information as to whether theredundancy replacement should be conducted and an address where suchredundancy replacement is to be conducted are recorded in a non-volatilemanner, according to the connected/disconnected patterns of fuseelements.

It should be understood, however, that the configuration of fuse programcircuit is not limited to that shown in FIG. 18.

FIG. 20 is a circuit diagram illustrating a configuration of anotherconventional fuse program circuit 800.

Fuse program circuit 800 includes: a capacitor C1 provided between anode N1 and a power supply potential Vcc; a fuse element F1 providedbetween node N1 and a ground potential GND; a P channel MOS transistorQP1 provided between node N1 and a power supply potential Vcc; and aninverter INV1 that receives and inverts the potential of node N1 andsupplies its output to a gate of the transistor QP1.

Transistor QP1 and inverter INV1 constitute a half latch.

The output of inverter INV1 is applied to a node N2, which becomes anoutput potential of fuse program circuit 800. The potential level ofnode N2 is at an H level when the fuse is not blown, and becomes an Llevel when the fuse is blown.

Thus, fuse program circuit 800 shown in FIG. 20 has fundamentally thesame configuration as fuse program circuit 810 shown in FIG. 18, exceptthat polarities of the transistors are complementary to each other and,in response, the circuit configuration has been modified.

Now, disadvantages in the operations of these circuits will beexplained, first as to the circuit shown in FIG. 20.

In general, fuse element F1 of FIG. 20 is made of polycrystallinesilicon (polysilicon) or metal interconnection.

Fuse element F1 is normally disconnected as follows. Laser light isilluminated onto fuse element F1 to locally raise the temperature of thefuse, thereby causing fuse element F1 itself to evaporate.

A resistance of fuse element F1 before laser illumination is at most 10KΩ, although it varies dependent on the material being used.

Raising the resistance of fuse element F1 by laser illumination to anopen state, i.e., at least 1GΩ, corresponds to blowing of the fuse. Fuseprogram circuit 800 serves to recognize such a large change inresistance of the fuse.

There are some cases where the fuse material is not completelyevaporated by laser illumination, for example, due to displacement offocus of laser light, variation in thickness of an insulating filmdeposited on the fuse, or subtle misalignment of the location to beilluminated, which causes a small portion of the fuse material toremain. In this case, fuse element F1 does not acquire a completely openstate even after the laser illumination, with a high-resistancecomponent being left. Hereinafter, such a remaining portion is called a“blown fuse remainder”.

The structure of fuse element and disadvantages at the time of laserillumination are disclosed, for example, in Japanese Patent Laying-OpenNo. 10-340956 and Japanese Patent Laying-Open No. 11-17010.

At the time of mass production, there are cases where it is difficult tostabilize the high-resistance component due to the blown fuse remainderconstantly at a level at least 10 MΩ.

Fuse program circuit 800 shown in FIG. 20 is designed in such a way thatthe output level becomes an H level when fuse element F1 is not blownand an L level when fuse element F1 is blown.

Hereinafter, the case where there exists a high-resistance component ofabout 10 MΩ as the remainder of blown fuse element F1 will beconsidered.

Here, assume that power supply potential Vcc rises very slowly afterpower-on. In this case, capacitor C1 may not work effectively to setnode N1 to an H level, and thus, the level of node N1 may be an L leveleven if the fuse is blown. In such a case, the output level of fuseprogram circuit 800 attains an H level, which leads to a malfunction.

Further, when the high-resistance component of about 10 MΩ exists, evenif the level of node N1 becomes an H level and the output level of fuseprogram circuit 800 attains an L level assuring a normal operation,there may arise another problem that a stand-by current above a standardlevel flows.

More specifically, a leakage path for the current may be created throughtransistor QP1 connected to node N1, via the high resistance of theblown fuse remainder, towards ground potential GND. If power supplypotential Vcc=3V, for example, the current value due to such a leakagepath becomes I=V/R=3V/10MΩ=0.3 μA.

In recent years, a requirement for the stand-by current for a staticsemiconductor memory device (SRAM), for example, has become extremelystringent. A standard value of such a stand-by current is, e.g., on theorder of 1 μA. Therefore, if an SRAM includes four blown fuses eachhaving a high-resistance component left as the blown fuse remainder ofabout 10 MΩ, the SRAM immediately becomes below standards, therebydecreasing the yield.

Similarly, fuse program circuit 810 shown in FIG. 18 is designed suchthat its output level becomes an L level when the fuse is not blown andan H level when the fuse is blown.

In this case, again, assume that there exists the blown fuse remainder.If power supply potential Vcc rises very slowly after power-on, as inthe case of FIG. 20, capacitor C1 will not work effectively to causenode N1 to attain an L level. Accordingly, due to the high-resistancecomponent as the blown fuse remainder, node N1 will attain an H level,the output level of fuse program circuit 810 will become an L level,thereby causing a malfunction.

Even in the case where node N1 becomes an L level after blowing thefuse, and even if the output level of fuse program circuit 810 becomesan H level and a normal operation is conducted, a stand-by current willinevitably flow from power supply potential Vcc via the high resistanceof the blown fuse remainder towards transistor QN1. This again decreasesthe yield.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a program circuit thathas a high operating margin against leakage of a conduction settingelement, e.g., leakage due to a blown fuse remainder, and that iscapable of suppressing a stand-by current

Another object of the present invention is to provide a semiconductormemory device that has a high operating margin against leakage of aconduction setting element, e.g., leakage due to a blown fuse remainder,and that is capable of suppressing a stand-by current.

In summary, the present invention is a program circuit that includes asignal generating circuit, a first internal node, a drive circuit, asecond internal node, a third switch circuit and a potential retainingcircuit.

The signal generating circuit generates a first trigger signal and asecond trigger signal that is delayed by a prescribed time from thefirst trigger signal.

The drive circuit operates by receiving a first power supply potentialand a second power supply potential that is different from the firstpower supply potential, and drives the potential of the first internalnode. The drive circuit includes a first switch circuit, a conductionsetting element and a second switch circuit. The first switch circuit isprovided within a first path extending from the second power supplypotential to the first internal node, and attains a conductive orshutdown state according to the first trigger signal. The conductionsetting element is provided within the first path in series with thefirst switch circuit. It can be externally set to either a conductive ornon-conductive state in a non-volatile manner. The second switch circuitis provided within a second path extending from the first power supplypotential to the first internal node. It attains a conductive orshutdown state according to the first trigger signal, complementarily tothe first switch circuit.

The third switch circuit causes the first internal node and the secondinternal node to attain a conductive or shutdown state according to thesecond trigger signal. The potential retaining circuit operates byreceiving the first and second power supply potentials. It retains thepotential level of the second internal node and outputs the same.

The present invention according to another aspect is a semiconductormemory device that includes a memory cell array, a normal memory cellselect circuit and a redundant memory cell select circuit.

A plurality of memory cells are arranged in the memory cell array. Thememory cell array includes a plurality of normal memory cells, and aplurality of spare memory cells for recovery of the normal memory cells.The normal memory cell select circuit selects a normal memory cellaccording to an address signal. The redundant memory cell select circuitprestores a defective address having a defective memory cell, andselects a spare memory cell instead of the normal memory cell accordingto the address signal.

The redundant memory cell select circuit includes a program circuit forstoring the defective address in a non-volatile manner.

The program circuit includes a signal generating circuit, a firstinternal node, a drive circuit, a second internal node, a third switchcircuit and a potential retaining circuit.

The signal generating circuit generates a first trigger signal and asecond trigger signal that is delayed by a prescribed time from thefirst trigger signal.

The drive circuit operates by receiving a first power supply potentialand a second power supply potential that is different from the firstpower supply potential, and drives the potential of the first internalnode. The drive circuit includes a first switch circuit, a conductionsetting element, and a second switch circuit. The first switch circuitis provided within a first path extending from the second power supplypotential to the first internal node, and attains a conductive orshutdown state according to the first trigger signal. The conductionsetting element is provided within the first path in series with thefirst switch circuit, and can be externally set to either a conductiveor non-conductive state in a non-volatile manner. The second switchcircuit is provided within a second path extending from the first powersupply potential to the first internal node, and is set to a conductiveor shutdown state according to the first trigger signal, complementarilyto the first switch circuit.

The third switch circuit causes the first and second internal nodes toattain a conductive or shutdown state according to the second triggersignal. The potential retaining circuit operates by receiving the firstand second power supply potentials, and retains the potential level ofthe second internal node for output.

Accordingly, the present invention has advantages that, despite leakageof the conduction setting element, e.g., leakage due to the remainder ofblown fuse element, the third switch circuit shuts down the leakagepath, so that it is possible to set a high operating margin against theblown fuse remainder, and to suppress a stand-by current.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an exemplary configuration of a fuseprogram circuit 820 capable of suppressing a malfunction due to a blownfuse remainder.

FIG. 2 is a timing chart illustrating an operation of fuse programcircuit 820.

FIG. 3 is a timing chart illustrating the operation of fuse programcircuit 820 in the case where the fuse F2 is blown.

FIG. 4 is a timing chart illustrating an output waveform in the casewhere a reset signal generating circuit 830 generates a power on resetsignal POR.

FIG. 5 is a schematic block diagram showing a configuration of asemiconductor memory device 1000 according to a first embodiment of thepresent invention.

FIG. 6 is a circuit diagram showing a configuration of a fuse programcircuit 100.

FIG. 7 is a timing chart illustrating an operation of fuse programcircuit 100.

FIG. 8 is a timing chart illustrating the operation of fuse programcircuit 100 in the case where a fuse element F100 is blown.

FIG. 9 is a timing chart illustrating the operation of fuse programcircuit 100 in the case where there exists a blown fuse remainder.

FIG. 10 is a waveform chart illustrating changes of power on resetsignal POR and a signal PORD.

FIG. 11 is a circuit diagram showing another configuration of aninverter INV10 in the configuration of fuse program circuit 100.

FIG. 12 is a circuit diagram showing a configuration of a fuse programcircuit 200 according to a second embodiment of the present invention.

FIG. 13 is a timing chart illustrating an operation of fuse programcircuit 200.

FIG. 14 is a timing chart illustrating the operation of fuse programcircuit 200 in the case where a fuse element F200 is blown.

FIG. 15 is a timing chart illustrating the operation of fuse programcircuit 200 in the case where there exists a blown fuse remainder.

FIG. 16 is a circuit diagram showing another configuration of aninverter INV30 in the configuration of fuse program circuit 200.

FIG. 17 is a block diagram showing a configuration of a main portion ofa conventional semiconductor memory device including a redundantcircuit.

FIG. 18 is a circuit diagram showing a configuration of a fuse programcircuit 810 included in a redundancy select circuit 3.

FIG. 19 is a circuit diagram showing a detailed configuration of areplacement address program circuit 4.

FIG. 20 is a circuit diagram showing a configuration of anotherconventional fuse program circuit 800.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

Program Circuit Resistant to Blown Fuse Remainder

FIG. 1 is a circuit diagram showing an exemplary configuration of a fuseprogram circuit 820 that is capable of suppressing a malfunction due tothe blown fuse remainder as described above.

Fuse program circuit 820 includes: an inverter circuit INV20 thatreceives an output signal from a reset signal generating circuit 830 andhas its output level changeable according to whether a fuse element isblown or not; and a half latch circuit HLT10 that receives and retainsthe output of inverter INV20 and generates an output of fuse programcircuit 820.

Inverter INV20 includes a P channel MOS transistor QP22, a fuse elementF2 and an N channel MOS transistor QN22 that are connected in seriesbetween a power supply potential Vcc and a ground potential GND.

The gates of transistors QP22 and QN22 both receive a reset signal RSTfrom reset signal generating circuit 830.

A connect node between fuse element F2 and transistor QN22 correspondsto the output node N1 of inverter INV20.

Half latch circuit HLT10 includes an N channel MOS transistor QN21provided between node N1 and a ground potential GND, and an inverterINV21 that receives and inverts the potential level of node N1 andsupplies its output to the gate of transistor QN21.

The output of inverter INV21 is supplied to the output node N2 as theoutput level of fuse program circuit 820.

As will be described below, the reset signal generating circuit 830shown in FIG. 1 may be configured to generate the reset signal RST basedon an externally supplied control signal, or to generate the power onreset signal POR according to a rise of power supply potential Vcc afterpower-on. The configuration of the power on reset circuit generatingsuch a power on reset signal is disclosed, for example, in U.S. Pat. No.5,703,510.

The fuse program circuit 820 shown in FIG. 1 uses a signal supplied fromthis reset signal generating circuit 830, so that it is unlikely tosuffer a malfunction due to the blown fuse remainder even in the casewhere the power supply potential Vcc rises very slowly.

Fuse program circuit 820 is designed such that its output becomes an Llevel when the fuse is not blown and an H level when the fuse is blown.

FIG. 2 is a timing chart illustrating the operation of fuse programcircuit 820 shown in FIG. 1. It is assumed that fuse element F2 is notblown in FIG. 2.

Referring to FIG. 2, after power supply potential Vcc completely risesto a prescribed level at time t0, external reset signal RST attains an Hlevel at time t1. It maintains the H level until time t2. The timeperiod from t1 to t2 during which signal RST is held at the H level iscalled a period PA.

When reset signal RST attains the H level at time t1, in fuse programcircuit 820 with its fuse element F2 having not been blown, transistorsQP22 and QN22 operate as an inverter and node N1 attains an L level.Thus, the output level of fuse program circuit 820 becomes an H level.

At time t2, when signal RST attains an L level, node N1 attains an Hlevel, and the output level of fuse program circuit 820 becomes an Llevel.

Hereinafter, a time period after time t2 wherein signal RST is at an Llevel is called a period PB.

FIG. 3 is a timing chart illustrating the operation of fuse programcircuit 820 shown in FIG. 1 in the case where fuse F2 is blown.

When reset signal RST attains an H level at time t1, irrespective of thestate of fuse element F2, transistor QN22 turns on, so that node N1attains an L level. In response thereto, the output level of fuseprogram circuit 820 becomes an H level. Further, transistor QN21 isrendered conductive, and the output level of half latch circuit HLT10 isretained at an H level.

At time t2, reset signal RST attains an L level. Since fuse element F2has been blown, node N1 is not charged even though transistor QP22 turnson, and thus, node N1 maintains the L level. Accordingly, the outputlevel of fuse program circuit 820 also maintains the H level.

Here, even if there exists a high-resistance component due to theremainder of blown fuse F2, transistor QN21 of half latch circuit HLT10is at an ON state. Therefore, if the ON resistance of transistor QN21 issufficiently smaller than the high-resistance component of the blownfuse remainder, the level of node N1 will not exceed the logicalthreshold value of inverter INV20.

For example, the ON resistance of transistor QN21 normally is notgreater than 100KΩ. This is sufficiently lower than the typical value of10MΩ of the remainder of blown fuse element.

Accordingly, in this case, fuse program circuit 820 is prevented frommalfunctioning even in the presence of the blown fuse remainder.

A semiconductor memory device, e.g., SRAM, using fuse program circuit820 as shown in FIG. 1 comes to operate with its defective memory cellbeing replaced during period PB, i.e., after a pulse of an H level isinput as reset signal RST and while it maintains the L level.

In FIG. 1, a signal that is input into inverter INV20 is not limited tothe reset signal RST that is generated based on an external controlsignal. It may be a power on reset signal POR that is generated by resetsignal generating circuit 830 in response to a rise of power supplypotential Vcc.

FIG. 4 is a timing chart illustrating an output waveform in the casewhere reset signal generating circuit 830 shown in FIG. 1 generates thepower on reset signal POR.

Referring to FIG. 4, reset signal generating circuit 830 has a potentiallevel that is identical to the power supply potential Vcc from power-onat time t1 when the power supply potential Vcc starts to rise, until itreaches a prescribed potential VR at time t2.

This time period from time t1 to time t2 is also called a period PA.

When power supply potential Vcc exceeds the prescribed potential VRafter time t2, reset signal generating circuit 830 drives power on resetsignal POR as its output signal to an L level. The time period aftertime t2, i.e., after power supply potential Vcc has exceeded theprescribed potential VR, is also called a period PB.

Even if power on reset signal POR changes as shown in FIG. 4 during theperiods PA and PB in FIG. 4, fuse program circuit 820 operates in thesame manner as in the periods PA and PB shown in FIGS. 2 and 3.

Thus, fuse program circuit 820 shown in FIG. 1 exhibits a very highoperating margin against the blown fuse remainder. However, it stillposes the problem of the stand-by current.

Specifically, in the case where there exists a high-resistance componentof 10MΩ due to the blown fuse remainder and still fuse program circuit820 normally operates, node N1 is at an L level during the operatingperiod PB. Thus, the stand-by current inevitably flows from transistorQP22 via the blown fuse remainder towards transistor QN21.

Therefore, the semiconductor integrated circuit device, e.g., SRAM,employing such fuse program circuit 820 still suffers the problem thatits stand-by current is not restricted within the standard value, whichdecreases the yield.

Configuration Capable of Suppressing Stand-by Current

FIG. 5 is a schematic block diagram showing a configuration of asemiconductor memory device 1000 according to the first embodiment ofthe present invention. Semiconductor memory device 1000 is formed on achip CH.

Although the configuration and operation of a semiconductor memorydevice will now be described, taking an SRAM as an example, the presentinvention is not limited thereto. It may generally be applied to anysemiconductor integrated circuit device that has a program circuitallowing pre-recording of data in a non-volatile manner.

Referring to FIG. 5, semiconductor integrated circuit device 1000includes a plurality of memory blocks, of which only two memory blocksBKa and BKb are shown representatively. Memory block BKa includes amemory cell array block 1 a, a decoder 2 a, a sense amplifier unit 13 aand a sense amplifier activating circuit 8 a. Similarly, memory blockBKb includes a memory cell array block 1 b, a decoder 2 b, a senseamplifier unit 13 b and a sense amplifier activating circuit 8 b.

Each memory cell array block 1 a, 1 b includes a plurality of word linesWL, a plurality of bit line pairs BL, and a plurality of memory cells MCprovided at their respective crossing points. Each sense amplifier unit13 a, 13 b includes a plurality of sense amplifiers connected to theplurality of bit line pairs BL, a plurality of transfer gates (notshown), a decoder and a write driver.

A replacement circuit 10 a and a redundant word line RWLa are providedcorresponding to memory block BKa, and a replacement circuit 10 b and aredundant word line RWLb are provided corresponding to memory block BKb.Redundant memory cells MC are connected to respective redundant wordlines RWLa, RWLb.

Replacement circuit 10 a includes a redundancy select circuit 3 a, areplacement address program circuit 4 a, a NAND circuit 5 a, and aninverter 6 a. Similarly, replacement circuit 10 b includes a redundancyselect circuit 3 b, a replacement address program circuit 4 b, a NANDcircuit 5 b, and an inverter 6 b.

Replacement circuit 10 a and redundant word line RWLa constitute aredundancy circuit corresponding to memory block BKa. Replacementcircuit 10 b and redundant word line RWLb constitute a redundancycircuit corresponding to memory block BKb. The configuration andoperation of each redundancy select circuit 3 a, 3 b are basicallyidentical to the configuration and operation of redundancy selectcircuit 3 shown in FIG. 18, except for the configuration of the fuseprogram employed therein as will be described later.

The configuration and operation of each replacement address programcircuit 4 a, 4 b are basically identical to those of replacement addressprogram circuit 4 shown in FIG. 19, except for the configuration of thefuse program employed therein as will be described later.

A normal memory cell non-select circuit 11 is further provided commonlyto all the memory blocks BKa, BKb. Normal memory cell non-select circuit11 includes a NAND circuit 7 and an inverter 8.

Semiconductor memory device 1000 further includes a pre-decoder 12.Pre-decoder 12 pre-decodes a plurality of X address signals XA andgenerates a plurality of pre-decode signals PXA. Pre-decoder 12 alsopre-decodes a plurality of Y address signals YA and generates aplurality of pre-decode signals PYA. Pre-decoder 12 further pre-decodesa plurality of Z address signals ZA and generates a plurality ofpre-decode signals PZA.

The plurality of pre-decode signals PXA are applied to each decoder 2 a,2 b and also to each replacement address program circuit 4 a, 4 b.Pre-decode signals PYA are applied to each sense amplifier unit 13 a, 13b. Pre-decode signals (block address signals) PZA are applied to a blockselector 9 and also to each replacement address program circuit 4 a, 4b.

Semiconductor memory device 1000 further includes a reset signalgenerating circuit 30 that responds to a control signal externallysupplied via a terminal 15 and generates a reset signal RST and a signalRSTD delayed by a prescribed time from reset signal RST.

Replacement address program circuits 4 a, 4 b and redundancy selectcircuits 3 a, 3 b all operate by receiving signals RST and RSTD.

It is understood that reset signal generating circuit 30 may beconfigured in such a way that it responds to a rise of power supplypotential Vcc to generate a power on reset signal POR and a signal PORDdelayed by a prescribed time from the signal POR, as will be describedlater.

FIG. 6 is a circuit diagram showing a configuration of fuse programcircuit 100 for use in redundancy select circuits 3 a and 3 b andreplacement address program circuits 4 a and 4 b shown in FIG. 5.

Fuse program circuit 100 includes: an inverter INV10 that receives resetsignal RST as an output from reset signal generating circuit 30, anddrives the potential level of node Ni according to whether the fuseelement is blown or not; a transfer gate TG10 that is provided betweennode N1 and node N2 and causes nodes N1 and N2 to enter a conductive orshutdown state according to the delayed reset signal RSTD from resetsignal generating circuit 30; and a latch circuit LT10 that is providedbetween node N2 and output node N3 and latches the potential level ofnode N2 and outputs an inverted level of the potential level of node N2to node N3.

Reset signal generating circuit 30 includes: a reset circuit 32 thatgenerates a reset signal in response to an external control signal; anda delay circuit 34 that receives an output of reset circuit 32 anddelays the signal by a prescribed time to output as a delayed resetsignal RSTD.

Inverter INV10 includes a P channel MOS transistor QP100, a fuse elementF100 and an N channel MOS transistor QN100 that are connected in seriesbetween power supply potential Vcc and ground potential GND.

The gates of transistors QP100 and QN100 receive signal RST from resetsignal generating circuit 30. A connect node between fuse element F100and transistor QN100 is connected to node N1.

It should be understood that reset circuit 32 within reset signalgenerating circuit 30 may be configured to buffer the externallysupplied reset signal RST before output, as described above. Resetsignal generating circuit 30 may also be configured to generate power onreset signal POR and signal PORD changing after a prescribed time ofdelay from signal POR. Further, reset signal generating circuit 30 maybe configured such that it provides fuse program circuit 100 with, asthe reset signal RST, a signal that corresponds to a logical OR of asignal obtained by buffering externally supplied reset signal RST and apower on reset signal, and also provides fuse program circuit 100 with,as the delayed reset signal RSTD, a signal that is obtained by delayingthe reset signal RST corresponding to the logical OR by a prescribedtime.

Hereinafter, reset circuit 32 will be described, first assuming that itis configured to buffer externally supplied reset signal RST beforeoutput.

Transfer gate TG10 includes: an inverter INV100 that receives andinverts a signal RSTD output from delay circuit 34; an N channel MOStransistor TN100 connected between node N1 and node N2 and having itsgate receiving signal RSTD); and a P channel MOS transistor TP100provided between node N1 and node N2 and having its gate receiving anoutput of inverter INV100.

Latch circuit LT10 includes: an inverter INV101 that receives apotential level of node N2 as its input and supplies its output signalto a node N3 being an output node of fuse program circuit 100; and aninverter INV102 that receives a potential level of inverter INV101 asits input and supplies its output to an input node of inverter INV101.Inverters INV101 and 102 are CMOS inverters that operate by receivingpower supply potential Vcc and ground potential GND.

Fuse program circuit 100 is designed in such a way that its output levelbecomes an L level when the fuse is not blown and an H level when thefuse is blown.

FIG. 7 is a timing chart illustrating the operation of fuse programcircuit 100 shown in FIG. 6.

As described above, it is assumed that fuse program circuit 100 isprovided with reset signal RST and delayed reset signal RSTD from resetsignal generating circuit 30. In FIG. 7, the operation of fuse programcircuit 100 in the case where fuse element F100 is not blown isillustrated.

Referring to FIG. 7, after power supply potential Vcc completely risesto a prescribed potential level at time t0, reset signal RST output fromreset signal generating circuit 30 attains an H level at time t1.

Since transfer gate TG10 is at an OFF state during a time period from t0to t1 before reset signal RST attains the H level, latch circuit LT10maintains data at the time of power-up, i.e., undefined data.

When signal RST attains the H level at time t1, as fuse element F100 hasnot been blown, transistors QP100 and QN100 operate as an inverter andnode N1 attains an L level.

Signal RSTD output from delay circuit 34 is a delayed version of signalRST. This signal RSTD attains an H level at time t2, delayed by a timeΔt from the transition edge of signal RST from the L level to the Hlevel. Transfer gate TG10 is rendered conductive at this time.

Hereinafter, the time period from t2 to t3 wherein signals RST and RSTDare both at an H level will be called a period PA.

During this period PA, node N1 is at an L level and transfer gate TG10is conductive. Thus, the potential level of node N1 is transmitted tonode N2, and therefore, the potential level of node N2 attains an Llevel, and the output level of fuse program circuit 100, i.e., the levelof node N3, becomes an H level.

Signal RST falls to an L level at time t3, while signal RSTD maintainsthe H level until time t4. This time period from t3 to t4 will be calleda period PC.

During this period PC, node N1 changes from the L level to the H level,and the potential level is transmitted to node N2. Thus, the potentiallevel of node N2 becomes an H level, and the output level of fuseprogram circuit 100 becomes an L level.

Further, at time t4, signals RST and RSTD both become an L level. Thetime period after t4 will be called a period PB.

During this period PB, transfer gate TG10 is shut down, and latchcircuit LT10 maintains the potential level of node N2 during period PC.Thus, as in period PC, node N2 is at an H level and output node N3 is atan L level.

FIG. 8 is a timing chart illustrating the operation of fuse programcircuit 100 shown in FIG. 6 in the case where fuse element F100 isblown.

Here, the definitions of periods PA, PB and PC are assumed to be thesame as in the case of FIG. 7.

During period PA (from t2 to t3) wherein both signals RST and RSTD areat an H level, transistor QN 100 is rendered conductive and node N1becomes an L level. Transfer gate TG10 is rendered conductive, and nodeN2 also becomes an L level. Thus, the level at output node N3 becomes anH level.

Next, during period PC (from t3 to t4) wherein signal RST attains an Llevel and signal RSTD maintains the H level, node N1 cannot be chargedeven though transistor QP100 turns on, as fuse F100 has been blown.Therefore, node N1 maintains the L level and, as transfer gate TG10 isconductive, the potential level at node N2 is at an L level. Thus, thelevel at output node N3 maintains the H level.

During period PB (after t4) wherein both signals RST and RSTD attain anL level, transfer gate TG10 is shut down. Since latch circuit LT10maintains the potential level at node N2 during period PC, the level atnode N2 is at the L level and the level at output node N3 is at the Hlevel, as in period PC.

FIG. 9 is a timing chart illustrating the operation of fuse programcircuit 100 shown in FIG. 6 in the case where, although fuse elementF100 has been blown, there exists its remainder of high resistance.

During period PA (from t2 to t3), irrespective of the state of fuseF100, transistor QN100 drives nodes Ni and N2 to an L level.

During period PC (from t3 to t4) wherein signal RST is at an L level andsignal RSTD is at an H level, even though transistor QP100 turns on,nodes N1 and N2 are maintained at the L level by inverter INV102 withinlatch circuit LT10, because of the high resistance of the blown fuseremainder.

The ON resistance of a pull-down MOS transistor (not shown) withininverter INV102 is not greater than 100KQ, which is sufficiently lowcompared to the resistance value of the blown fuse remainder that is onthe order of 10 MΩ. Therefore, nodes N1 and N2 cannot be charged to thelevel greater than the logical threshold value of inverter INV101.Accordingly, nodes N1 and N2 maintain the L level, and output node N3maintains the H level.

Further, during period PB (after t4) wherein both signals RST and RSTDattain an L level, transfer gate TG10 is shut down, and latch circuitLT10 retains the state during period PC. Thus, as in period PC, node N2is at an L level and output node N3 maintains the H level.

During this period PB, as transfer gate TG10 is shut down, node N1cannot be maintained at the L level. Node N1 is slowly charged viatransistor QP100 in the ON state, through the blown fuse remainder.Since transfer gate TG10 is at an OFF state, however, it does not affectthe state of latch circuit LT10. Output level N3 thus maintains the Hlevel.

This period PB corresponds to a period in which semiconductor integratedcircuit device 1000 is in a normal operation mode. What is needed isonly that the stand-by current of semiconductor integrated circuitdevice 1000 using this fuse program circuit 100 meets its standardsduring this period.

During period PB, even if there exists a blown fuse remainder, therewill not occur any problem of stand-by current, as a current-flowingpath does not exist.

Next, assume that reset signal generating circuit 30 generates power onreset signal POR and signal PORD that changes after a prescribed time ofdelay from signal POR. FIG. 10 is a waveform chart that shows changes ofthe power on reset signal POR and the signal PORD.

During the power-up operation of power supply potential Vcc, resetsignal generating circuit 30 outputs signal POR at the same level aspower supply potential Vcc from time t1 to time t2 (during period PA)until power supply potential Vcc reaches a certain value VR.

Once power supply potential Vcc exceeds the potential VR at time t2,signal POR changes to an L level.

Signal PORD changes from the level of power supply potential Vcc to an Llevel at time t3 that is delayed by an amount of time At from time t2.

Periods PA, PB and PC shown in FIG. 10 correspond to periods PA, PB andPC shown in FIGS. 7-9, respectively. Even upon receipt of such signalPOR, fuse program circuit 100 operates in the same manner as explainedin conjunction with FIGS. 7-9.

In FIG. 10, signal PORD has been shown to rise above potential VR beforechanging to the L level. Alternatively, signal PORD may be the signalPOR simply delayed by a time Δt.

As explained above, fuse program circuit 100 shown in FIG. 6 not onlymaintains the characteristic that it has a high operating margin againstthe blown fuse remainder as in the conventional fuse program circuit820, but also has a characteristic that it prevents the stand-by currentfrom flowing even in the presence of such a blown fuse remainder.

Modification of First Embodiment

FIG. 11 is a circuit diagram illustrating another configuration ofinverter INV10 in the configuration of fuse program circuit 100 shown inFIG. 6.

Inverter INV10 includes a fuse element F100, a P channel MOS transistorQP100 and an N channel MOS transistor QN100 that are connected betweenpower supply potential Vcc and ground potential GND.

A connect node between transistor QP100 and transistor QN100 isconnected to node N. Fuse element F100 is provided between power supplypotential Vcc and a source of transistor QP100.

The gates of transistors QP100 and QN100 both receive signal RST fromreset signal generating circuit 30.

Using inverter INV10 having the configuration as shown in FIG. 11, fuseprogram circuit 100 can operate completely in the same manner as in thecase of the configuration shown in FIG. 6.

Second Embodiment

FIG. 12 is a circuit diagram illustrating a configuration of a fuseprogram circuit 200 according to the second embodiment of the presentinvention.

The configuration of fuse program circuit 200 is identical to theconfiguration of fuse program circuit 100 shown in FIG. 6, except thatinverter INV10 including fuse element F100 has been replaced with aninverter INV30 including a fuse element F200, and that another inverterINV32 is provided such that inverter INV30 receives a signal (signal/POR or signal /RST) that is an inverted version of the signal in thecase of fuse program circuit of FIG. 6.

More specifically, fuse program circuit 200 includes: an inverter INV32that receives and inverts reset signal RST output from reset signalgenerating circuit 30 (not shown); an inverter INV30 that receives anoutput from inverter INV32, and drives the potential level of node N1according to whether the fuse element is blown or not; a transfer gateTG10 provided between node N1 and node N2 for causing node N1 and nodeN2 to enter a conductive or shutdown state according to the delayedreset signal RSTD from reset signal generating circuit 30 (not shown);and a latch circuit LT10 provided between node N2 and output node N3 forlatching the potential level at node N2 and outputting an inverted levelof the potential level of node N2 to node N3.

It is assumed that reset signal generating circuit 30 has aconfiguration identical to that in the first embodiment.

Inverter INV30 includes a P channel MOS transistor QP200, a fuse elementF200 and an N channel MOS transistor QN200 that are connected in seriesbetween power supply potential Vcc and ground potential GND.

The gates of transistors QP200 and Qn2OO receive signal /RST frominverter INV32. A connect node between fuse element F200 and transistorQP200 is connected to node N1.

The configurations of transfer gate TG10 and latch circuit LT10 areidentical to those described in the first embodiment, and therefore,same reference characters denote same or corresponding portions anddetailed description thereof is not repeated.

Fuse program circuit 200 is configured such that it has an output levelof an H level when the fuse is not blown and an L level when the fuse isblown.

FIG. 13 is a timing chart illustrating the operation of fuse programcircuit 200 shown in FIG. 12, which corresponds to FIG. 7 of the firstembodiment. FIG. 13 shows the operation in the case where fuse elementF200 in the configuration of fuse program circuit 200 is not blown.

FIG. 14 is a timing chart illustrating the operation of fuse programcircuit 200 shown in FIG. 12 in the case where fuse element F200 isblown. This corresponds to FIG. 8 in the first embodiment.

Further, FIG. 15 is a timing chart illustrating the operation of fuseprogram circuit 200 shown in FIG. 12 in the case where, although fuseelement F200 has been blown, there exists its remainder of highresistance. This corresponds to FIG. 9 in the first embodiment.

In FIGS. 13-15, the output level of inverter INV30 (potential level ofnode N1) and the potential level of output node N3 are inverted withrespect to those in FIGS. 7-9. Otherwise, the operations are identicalto those in the first embodiment, and therefore, detailed descriptionthereof will not be repeated.

In fuse program circuit 200 shown in FIG. 12, as in the first embodimentshown in FIG. 10, reset signal generating circuit 30 may be configuredsuch that it generates power on reset signal POR and signal PORD toallow fuse program circuit 200 to operate. Further, reset signalgenerating circuit 30 may be configured such that it applies to fuseprogram circuit 200, as reset signal RST, a signal equivalent to alogical OR of the power on reset signal and a signal obtained bybuffering the externally supplied reset signal RST, and also applies tofuse program circuit 200, as delayed reset signal RSTD, a signalobtained by delaying the reset signal RST equivalent to the logical ORby a prescribed time.

Fuse program circuit 200 shown in FIG. 12 again maintains the samecharacteristic as the conventional fuse program circuit 820 that it hasa high operating margin against the blown fuse remainder and further hasthe characteristic that it prevents the stand-by current from flowingeven in the presence of the blown fuse remainder.

Modification of Second Embodiment

FIG. 16 is a circuit diagram illustrating another configuration ofinverter INV30 in the configuration of fuse program circuit 200 shown inFIG. 12.

Inverter INV30 includes a P channel MOS transistor QP200, an N channelMOS transistor QN200 and a fuse element F200 that are connected betweenpower supply potential Vcc and ground potential GND.

A connect node between transistor QP200 and transistor QN200 isconnected to node Ni. Fuse element F200 is provided between groundpotential GND and a source of transistor QN200.

The gates of transistors QP200 and QN200 both receive the output signal/RST from inverter INV32 that inverts signal RST from reset signalgenerating circuit 30.

Using inverter INV30 having the configuration as shown in FIG. 16, fuseprogram circuit 200 can operate completely in the same manner as in thecase with the configuration shown in FIG. 12.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. A program circuit, comprising: a signalgenerating circuit generating a first trigger signal and a secondtrigger signal that is delayed by a prescribed time from said firsttrigger signal; a first internal node; a drive circuit operating byreceiving a first power supply potential and a second power supplypotential that is different from said first power supply potential fordriving a potential of said first internal node, said drive circuitincluding a first switch circuit provided in a first path extending fromsaid second power supply potential to said first internal node andattaining one of a conductive state and a shutdown state according tosaid first trigger signal, a conduction setting element provided in saidfirst path in series with said first switch circuit and configured to beexternally set to one of a conductive state and a non-conductive statein a non-volatile manner, and a second switch circuit provided in asecond path extending from said first power supply potential to saidfirst internal node and attaining one of a conductive state and ashutdown state, complementarily to said first switch circuit, accordingto said first trigger signal; a second internal node; a third switchcircuit responsive to said second trigger signal for driving said firstinternal node and said second internal node to one of a conductive stateand a shutdown state; and a potential retaining circuit operating byreceiving said first and second power supply potentials for retaining apotential level of said second internal node for output.
 2. The programcircuit according to claim 1, wherein said conduction setting elementincludes a fuse element provided such that it can be externally blown.3. The program circuit according to claim 1, wherein said potentialretaining circuit includes a first CMOS inverter having said secondinternal node and an input node coupled thereto, and a second CMOSinverter operating by receiving said first and second power supplypotentials for inverting an output of said first CMOS inverter to applythe inverted output to said second internal node.
 4. The program circuitaccording to claim 1, wherein said signal generating circuit generatessaid first and second trigger signals according to a control signalsupplied from an outside of said program circuit.
 5. The program circuitaccording to claim 1, wherein said signal generating circuit generatessaid first and second trigger signals in response to a rise of one ofsaid first and second power supply potentials.
 6. The program circuitaccording to claim 1, wherein said signal generating circuit generatessaid first and second trigger signals based on a logical OR of a firstsignal that is generated according to a control signal supplied from anoutside of said program circuit and a second signal that is generated inresponse to a rise of one of said first and second power supplypotentials.
 7. A semiconductor memory device, comprising: a memory cellarray having a plurality of memory cells arranged therein, said memorycell array including a plurality of normal memory cells and a pluralityof spare memory cells for recovery of said normal memory cells; a normalmemory cell select circuit for selecting said normal memory cell inresponse to an address signal; and a redundant memory cell selectcircuit for prestoring a defective address having a defective memorycell, and selecting said spare memory cell instead of said normal memorycell in response to said address signal, said redundant memory cellselect circuit including a program circuit for storing said defectiveaddress in a non-volatile manner, said program circuit including asignal generating circuit generating a first trigger signal and a secondtrigger signal that is delayed by a prescribed time from said firsttrigger signal, a first internal node, a drive circuit operating byreceiving a first power supply potential and a second power supplypotential that is different from said first power supply potential fordriving a potential of said first internal node, said drive circuitincluding a first switch circuit provided in a first path extending fromsaid second power supply potential to said first internal node andattaining one of a conductive state and a shutdown state according tosaid first trigger signal, a conduction setting element provided in saidfirst path in series with said first switch circuit and configured to beexternally set to one of a conductive state and a non-conductive statein a non-volatile manner, and a second switch circuit provided in asecond path extending from said first power supply potential to saidfirst internal node and attaining one of a conductive state and ashutdown state, complementarily to said first switch circuit, accordingto said first trigger signal, said program circuit further including asecond internal node, a third switch circuit responsive to said secondtrigger signal for driving said first internal node and said secondinternal node to one of a conductive state and a shutdown state, and apotential retaining circuit operating by receiving said first and secondpower supply potential for retaining a potential level of said secondinternal node and outputting a signal for specification of saiddefective address.
 8. The semiconductor memory device according to claim7, wherein said conduction setting element includes a fuse elementprovided such that it can be externally blown.
 9. The semiconductormemory device according to claim 7, wherein said potential retainingcircuit includes a first CMOS inverter having said second internal nodeand an input node coupled thereto, and a second CMOS inverter operatingby receiving said first and second power supply potentials for invertingan output of said first CMOS inverter to apply the inverted output tosaid second internal node.
 10. The semiconductor memory device accordingto claim 7, wherein said signal generating circuit generates said firstand second trigger signals according to a control signal that issupplied from an outside of said program circuit.
 11. The semiconductormemory device according to claim 7, wherein said signal generatingcircuit generates said first and second trigger signals in response to arise of one of said first and second power supply potentials.
 12. Thesemiconductor memory device according to claim 7, wherein said signalgenerating circuit generates said first and second trigger signals basedon a logical OR of a first signal that is generated according to acontrol signal that is supplied from an outside of said program circuitand a second signal that is generated in response to a rise of one ofsaid first and second power supply potentials.